Generally, conventional processes for forming an isolating layer based on the local oxidation method (known as "LOCOS") has been continuously improved with respect to various aspects, and such improvements have been proposed in various forms. There has been, however, no satisfactory structure that addresses the shear stress due to the topology and at the same time reducing the size of the bird's beak. Further, in order to solve these two problems, the process often becomes complicated, and, therefore, such modified processes often are not suitable to be put to practical use.
FIGS. 1A-1C are partial sectional views illustrating a process for forming an isolating layer for a semiconductor device based on the conventional LOCOS method. FIGS. 1D and 1E illustrate the distributions of the shear stress which gives the greatest influence to the topology and the damage formation, and are based on a simulation that was performed using a process simulator known as "TSUPREM" for a state of the topology after the field oxidation. In the graph contour, the solid lines illustrate the case where the value of the shear stress is 1.times.E9 dyne/cm.sup.2 and 5.times.E9 dyne/cm.sup.2 while each of the intervals is 1.times.E9 dyne/cm.sup.2.
First, FIGS. 1A-1C illustrate the process for formation of an element isolating layer based on a semi-recessed oxide LOCOS method. This process includes the steps of: forming pad oxide layer 2 on silicon substrate I for buffering the difference in the thermal expansions of silicon and the nitride layer, and then, forming nitride layer 3 thereupon as an inter-layer insulating film; removing the relevant portions of nitride layer 3 and pad oxide layer 2 to open a field oxide layer region, and then carrying out a thermal oxidation to form field oxide layer 21; and removing nitride layer 3.
FIG. 1D is a graphical illustration showing the topology of the thin layer structure of a semiconductor, which is based on a simulation performed using the process simulator known as "TSUPREM 4" on the isolating layer of the semiconductor device formed with what is known as the semi-recessed oxide LOCOS method. The dotted lines illustrate the sectional structures of the nitride layer, the buffer oxide layer and the silicon substrate, before formation of the field oxide layer. The solid lines illustrate a field oxide layer formed as a result of the expansion of the volume of the buffer oxide layer during the thermal oxidation process, and also illustrate the formation of a bird's beak as a result of the expansion of the boundary portion between the nitride layer and the field oxide layer.
FIG. 1E illustrates the distribution of the shear stress which provides a decisive influence with respect to defect formation as a result of the formation of a bird's beak on the element isolating structure of the semiconductor device, when the semi-recessed oxide LOCOS method is applied. That is, due to a difference of the thermal expansions between the nitride layer and the silicon, shear stress is formed, and this stress is concentrated in the BB portion.
FIGS. 1F-1I are partial sectional views illustrating a process for formation of an isolating layer for a semiconductor device based on the LOCOS method. FIGS. 1J and 1K illustrate the distribution of the shear stress which provides a decisive influence with respect to the defect formation and to the topography, again which is based on a simulation using the process simulator known as "TSUPREM 4" in a topological state after the field oxidation. In the graph contour, the solid lines illustrate the case where the value of the shear stress is 1.times.E9 dyne/cm.sup.2 and 5.times.dyne/cm.sup.2, while each of the intervals is 1.times.E9 dyne/cm.sup.2.
FIGS. 1F-1I illustrate a process for formation of an element isolating layer for a semiconductor device based on a FRO (fully recessed oxide) LOCOS method. The process includes the steps of: forming pad oxide layer 12 on silicon substrate 11, then forming nitride layer 13 thereupon as an inter-layer insulating film, and then removing the relevant portions of the nitride layer and the pad oxide layer to open the field oxide layer portion; then again removing the open portion of silicon substrate 11 to a certain depth by an anisotropic etching process; carrying out a thermal oxidation to form field oxide layer 12' on the open portion of silicon substrate 11; and, then, removing nitride layer 13.
FIG. 1J is a graphical illustration showing the topology of the thin structure of a semiconductor device, again which is based on a simulation performed on the element isolating layer of a semiconductor device using a process simulator known as "TSUPREM 4" and by applying the FRO LOCOS method. The dotted lines illustrate the sectional structures of the nitride layer, the buffer oxide layer and the silicon substrate, before the formation of the field oxide layer. The solid lines show a field oxide layer formed by the expansion of the volume of the buffer oxide layer during the thermal oxidation, and also show the formation of a bird's beak on the nitride layer and the silicon substrate as a result of the thermal expansion of the boundary portion between the nitride layer and the field oxide layer.
FIG. 1K illustrates the distribution of the shear stress which provides a decisive influence with respect to the defect formation in an element isolating layer of a semiconductor device which is formed by applying the FRO LOCOS method. That is, due to the difference of the thermal expansion rates between the nitride layer and the silicon, shear stress is generated, and this shear stress is concentrated in the BB portion.
In the above described conventional techniques for forming an isolating layer for a semiconductor device, the problems of the size of the bird's beak and the minimizing of the shear stress cannot be resolved simultaneously. Further, the process becomes complicated due to increased use of masking operations.